The present invention relates generally to a method for simultaneously forming a through silicon via and a deep trench structure and, more specifically, to structures and methods for simultaneously forming a through silicon via and a deep trench capacitor or a deep trench isolation.
Through-silicon-via (TSV) is becoming a viable technology approach for improving chip performance at the system level by 3-D chip integration. On-chip decoupling capacitors are highly desired to suppress power fluctuation. Deep trench capacitors (DTCap) have a capacitance density advantage over other planar capacitors due to the fact that the capacitors can be formed in deep trenches in a semiconductor substrate. Furthermore, deep trench isolation (DTI) is becoming necessary for future CMOS technologies and beyond. Deep trench etching is very challenging and costly. The issue is exacerbated due to different and sometimes competing requirements of TSV, DTCap, and DTI. For example, TSV and DTI require a thick dielectric on the trench sidewall to provide sufficient insulation between the trench and the substrate and to reduce the parasitic capacitance. In contrast, DTCap requires a thin dielectric on the trench sidewall to maximize the capacitance gain in a deep trench capacitance. Given the high-aspect ratio of deep trenches, however, processing one type of trench (e.g., TSV) while protecting the other kind of trench (e.g., DTCap or DTI) is extremely challenging, if not all possible and is not cost-effective.